library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Entity declaration
entity mux4to1 is
    Port (
        sel : in  STD_LOGIC_VECTOR (1 downto 0); -- 2-bit select input
        d0  : in  STD_LOGIC_VECTOR (15 downto 0); -- Data input 0
        d1  : in  STD_LOGIC_VECTOR (15 downto 0); -- Data input 1
        d2  : in  STD_LOGIC_VECTOR (15 downto 0); -- Data input 2
        d3  : in  STD_LOGIC_VECTOR (15 downto 0); -- Data input 3
        y   : out STD_LOGIC_VECTOR (15 downto 0)  -- Output
    );
end mux4to1;

-- Architecture definition
architecture Behavioral of mux4to1 is
begin
    process(sel, d0, d1, d2, d3)
    begin
        case sel is
            when "00" =>
                y <= d0;
            when "01" =>
                y <= d1;
            when "10" =>
                y <= d2;
            when "11" =>
                y <= d3;
            when others =>
                y <= X"1111"; -- Default case, should not happen
        end case;
    end process;
end Behavioral;